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projekte:3cmbeacon:start [2023/01/06 18:30] thastiprojekte:3cmbeacon:start [2023/01/07 11:20] thasti
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 ===== Architecture ===== ===== Architecture =====
-{{ :projekte:3cmbeacon:odu_tx_ref.jpg?500|Fully assembled transmitter PCB on temporary heat sink}} 
- 
 A simple block diagram of the beacon transmitter is shown in the figure below. A simple block diagram of the beacon transmitter is shown in the figure below.
  
-~TODO~+{{ :projekte:3cmbeacon:hw_architecture.png?1090 |}}
  
 The beacon transmitter accepts an external 100 MHz reference clock provided by a GNSS-disciplined oscillator. GNSS stabilization is the de-facto standard for beacons on 10 GHz and above due to their narrow spacing and small bandwidth. It also enables receiving stations to use the beacon as a frequency reference for aligning their own equipment. The beacon transmitter accepts an external 100 MHz reference clock provided by a GNSS-disciplined oscillator. GNSS stabilization is the de-facto standard for beacons on 10 GHz and above due to their narrow spacing and small bandwidth. It also enables receiving stations to use the beacon as a frequency reference for aligning their own equipment.
 +
 +{{ :projekte:3cmbeacon:odu_tx_ref.jpg?500|Fully assembled transmitter PCB on temporary heat sink}}
  
 A Silicon Labs Si5342 is used as a crystal-driven reference PLL, which takes care of reference clock jitter cleaning and modulation generation. The high-resolution fractional divider allows synthesizing sub-Hz frequency steps of the output RF carrier, which are required for modern modulation formats. Due to the architecture of the synthesizer, no appreciable fractional spurs are generated in the process, yielding a very clean output spectrum with excellent phase noise. This IC generates in intermediate frequency of about 162 MHz, which is an integer multiplication factor lower than the final RF output frequency. A Linear LTC6948 RF PLL IC is used to multiply this signal by 16, up to a frequency of 2.592 GHz. From this point on, an Analog Devices HMC443 multiplier is used to create the final 10.368 GHz frequency. The multiplication creates some harmonic content at +-N*2.592 GHz away from the carrier, which are suppressed by a Mini-Circuits BFCN-Series MLCC bandpass filter. At this point, the final PA (Analog HMC952A) amplifies the signal up to around 1.5 W before reaching an SMA antenna connector. A Silicon Labs Si5342 is used as a crystal-driven reference PLL, which takes care of reference clock jitter cleaning and modulation generation. The high-resolution fractional divider allows synthesizing sub-Hz frequency steps of the output RF carrier, which are required for modern modulation formats. Due to the architecture of the synthesizer, no appreciable fractional spurs are generated in the process, yielding a very clean output spectrum with excellent phase noise. This IC generates in intermediate frequency of about 162 MHz, which is an integer multiplication factor lower than the final RF output frequency. A Linear LTC6948 RF PLL IC is used to multiply this signal by 16, up to a frequency of 2.592 GHz. From this point on, an Analog Devices HMC443 multiplier is used to create the final 10.368 GHz frequency. The multiplication creates some harmonic content at +-N*2.592 GHz away from the carrier, which are suppressed by a Mini-Circuits BFCN-Series MLCC bandpass filter. At this point, the final PA (Analog HMC952A) amplifies the signal up to around 1.5 W before reaching an SMA antenna connector.
projekte/3cmbeacon/start.txt · Zuletzt geändert: 2023/01/23 19:42 von thasti

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